FIG. 1 illustrates a conventional digital circuit 10 that receives four data bits (D0-D3) in parallel at four data input terminals, to form a 4-bit word, along with a clock at a fifth input terminal. The data is in non-return to zero (NRZ) code (no neutral states). The clock signal received by circuit 10 is typically the same clock signal used by the transmitter to clock out the data transmitted to the circuit 10.
In a typical circuit, the leading edge of the clock pulse acts as the trigger for input registers to store the data levels occurring at the time of the clock's leading edge. In FIG. 1, the input registers are D flip flops 12-15. In a D flip-flop, the data clocked in is applied at the Q output of the flip-flop at the leading edge of the clock pulse. Ideally, the data communication system is designed so that the leading edge of the clock (which triggers the input registers) occurs at about the midpoint between the data transition times to ensure that all the parallel data bits during a single cycle have transitioned, if at all, for that cycle.
FIG. 2A illustrates an example of a properly aligned clock, where the triggering edge occurs at about the midpoint between the data transition times. Only two data bits, D0 and D1, are shown for simplicity. If the propagation times were identical for all the data and clock paths, and the transmitter transmitted the clock and data signals with the alignment shown in FIG. 2A, then all sampled data will be accurate at the outputs of the flip-flops 12-15 (FIG. 1). As long as the leading edge of the clock occurs after all the data bits have transitioned, if at all, in a given data cycle, the 4-bit word stored in the registers will be accurate. Finite set-up and hold times of the data relative to the clock avoid metastable states but further reduce the valid data window.
When different propagation delays occur in the data and clock paths, proper input register clocking is not assured.
FIG. 2B illustrates the same transmitted signals as in FIG. 2A but where the propagation times of the data and clock signals are not the same. This may be due to different conductor lengths for the data and clock signals, or different loads on the clock and data lines, or different processing of the clock and data signals. In FIG. 2B, the leading edge of the clock signal has shifted outside of the valid data window due to different propagation delays during the transmission and/or reception of these three signals. Accordingly, in the example of FIG. 2B, the leading edge of the clock will trigger the input registers to store the D0 and D1 bits from two different data cycles, resulting in an incorrect 4-bit word clocked into and out of the input registers.
In the example of FIG. 1, the flip-flops 12-15 input the 4-bit word into a parallel-to-serial converter 18. A phase locked loop (PLL) clock multiplier 20 multiplies the input clock by 4×. The 4× clock is then used to clock out the serial data from a shift register, forming the output section of the converter 18, after each loading of a 4-bit word into the shift register.
What is needed is a circuit technique that can adjust a clock signal for triggering an input register, where the triggering edge of the clock signal is properly aligned or synchronized with the data transitions even when the data and clock paths have different propagation delays.